/*
 * File: explicitinvocation_funccallsubsys.c
 *
 * Code generated for Simulink model 'explicitinvocation_funccallsubsys'.
 *
 * Model version                  : 3.0
 * Simulink Coder version         : 9.5 (R2021a) 14-Nov-2020
 * C/C++ source code generated on : Wed Jan  5 11:48:01 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 * Validation result: Not run
 */

#include "explicitinvocation_funccallsubsys.h"

/* Block signals and states (default storage) */
DW rtDW;

/* External inputs (root inport signals with default storage) */
ExtU rtU;

/* External outputs (root outports fed by signals with default storage) */
ExtY rtY;

/* Model step function for TID1 */
void CallEvery2sAt1sPriority(void)  /* Explicit Task: CallEvery2sAt1sPriority */
{
  /* RootInportFunctionCallGenerator generated from: '<Root>/CallEvery2sAt1sPriority' incorporates:
   *  SubSystem: '<Root>/DataBuffer'
   */
  /* Inport: '<S1>/In1' */
  rtDW.Buffer = rtDW.Integrator;

  /* End of Outputs for RootInportFunctionCallGenerator generated from: '<Root>/CallEvery2sAt1sPriority' */
}

/* Model step function for TID2 */
void CallEvery1s(void)                 /* Explicit Task: CallEvery1s */
{
  /* RootInportFunctionCallGenerator generated from: '<Root>/CallEvery1s' incorporates:
   *  SubSystem: '<Root>/Rate1s'
   */
  /* Outputs for Atomic SubSystem: '<S2>/SS2' */
  /* Outport: '<Root>/Out2' incorporates:
   *  Gain: '<S5>/Gain'
   *  Inport: '<Root>/In1_1s'
   *  Sum: '<S5>/Sum'
   */
  rtY.Out2 = 2.0 * rtDW.Buffer + rtU.In1_1s;

  /* End of Outputs for SubSystem: '<S2>/SS2' */

  /* Outputs for Atomic SubSystem: '<S2>/SS1' */
  /* Outport: '<Root>/Out1' incorporates:
   *  Gain: '<S4>/Gain1'
   *  Gain: '<S4>/Gain2'
   *  Inport: '<Root>/In1_1s'
   *  Outport: '<Root>/Out2'
   *  Sum: '<S2>/Sum'
   *  Sum: '<S4>/Sum'
   */
  rtY.Out1 = (3.0 * rtDW.Buffer + rtU.In1_1s) * 5.0 + rtY.Out2;

  /* End of Outputs for SubSystem: '<S2>/SS1' */
  /* End of Outputs for RootInportFunctionCallGenerator generated from: '<Root>/CallEvery1s' */
}

/* Model step function for TID3 */
void CallEvery2s(void)                 /* Explicit Task: CallEvery2s */
{
  /* RootInportFunctionCallGenerator generated from: '<Root>/CallEvery2s' incorporates:
   *  SubSystem: '<Root>/Rate2s'
   */
  /* DiscreteIntegrator: '<S3>/Integrator' */
  rtDW.Integrator = rtDW.Integrator_DSTATE;

  /* Update for DiscreteIntegrator: '<S3>/Integrator' incorporates:
   *  Inport: '<Root>/In2_2s'
   */
  rtDW.Integrator_DSTATE += 2.0 * rtU.In2_2s;

  /* End of Outputs for RootInportFunctionCallGenerator generated from: '<Root>/CallEvery2s' */
}

/* Model initialize function */
void explicitinvocation_funccallsubsys_initialize(void)
{
  /* (no initialization code required) */
}

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
